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INTEGRATED CIRCUITS
PZ3064 64 macrocell CPLD
Product specification IC27 Data Handbook 1997 Mar 05
Philips Semiconductors
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
FEATURES
* Industry's first TotalCMOSTM PLD - both CMOS design and * Fast Zero Power (FZPTM) design technique provides ultra-low
power and very high speed process technologies
DESCRIPTION
The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZPTM) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZPTM design technique, the PZ3064 offers true pin-to-pin speeds of 10ns, while simultaneously delivering power that is less than 50A at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD - 70% lower at 50MHz. These devices are the first TotalCMOSTM PLDs, as they use both a CMOS process technology and the patented full CMOS FZPTM design technique. For 5V applications, Philips also offers the high speed PZ5064 CPLD that offers these features in a full 5V implementation. The Philips FZPTM CPLDs introduce the new patent-pending XPLATM (eXtended Programmable Logic Array) architecture. The XPLATM architecture combines the best features of both PLA and PALTM type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLATM structure in each logic block provides a fast 10ns PALTM path with 5 dedicated product terms per output. This PALTM path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 12.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The PZ3064 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools. The PZ3064 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.
* High speed pin-to-pin delays of 10ns * Ultra-low static power of less than 50A * Dynamic power that is 70% lower at 50MHz than competing * 100% routable with 100% utilization while all pins and all
macrocells are fixed devices
* Deterministic timing model that is extremely simple to use * 4 clocks with programmable polarity at every macrocell * Support for complex asynchronous clocking * Innovative XPLATM architecture combines high speed with * 1000 erase/program cycles guaranteed * 20 years data retention guaranteed * Logic expandable to 37 product terms * PCI compliant * Advanced 0.5 E2CMOS process * Security bit prevents unauthorized access * Design entry and verification using industry standard and Philips * Reprogrammable using industry standard device programmers * Innovative Control Term structure provides either sum terms or
product terms in each logic block for: - Programmable 3-State buffer - Asynchronous macrocell register preset/reset CAE tools extreme flexibility
* Programmable global 3-State pin facilitates `bed of nails' testing * Available in PLCC, TQFP, and PQFP packages * Available in both Commercial and Industrial grades
Table 1. PZ3064 Features
PZ3064 Usable gates Maximum inputs Maximum I/Os Number of macrocells Propagation delay (ns) Packages 2000 68 64 64 10 44-pin PLCC, 44-pin TQFP, 68-pin PLCC, 84-pin PLCC, 100-pin PQFP without using logic resources
PAL is a registered trademark of Advanced Micro Devices, Inc.
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853-1891 17824
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
ORDERING INFORMATION
ORDER CODE PZ3064-10A44 PZ3064-12A44 PZ3064I12A44 PZ3064I15A44 PZ3064-10BC PZ3064-12BC PZ3064I12BC PZ3064I15BC PZ3064-10A68 PZ3064-12A68 PZ3064I12A68 PZ3064I15A68 PZ3064-10A84 PZ3064-12A84 PZ3064I12A84 PZ3064I15A84 PZ3064-10BB1 PZ3064-12BB1 PZ3064I12BB1 PZ3064I15BB1 DESCRIPTION 44-pin PLCC, 10ns tPD 44-pin PLCC, 12ns tPD 44-pin PLCC, 12ns tPD 44-pin PLCC, 15ns tPD 44-pin TQFP, 10ns tPD 44-pin TQFP, 12ns tPD 44-pin TQFP, 12ns tPD 44-pin TQFP, 15ns tPD 68-pin PLCC, 10ns tPD 68-pin PLCC, 12ns tPD 68-pin PLCC, 12ns tPD 68-pin PLCC, 15ns tPD 84-pin PLCC, 10ns tPD 84-pin PLCC, 12ns tPD 84-pin PLCC, 12ns tPD 84-pin PLCC, 15ns tPD 100-pin PQFP, 10ns tPD 100-pin PQFP, 12ns tPD 100-pin PQFP, 12ns tPD 100-pin PQFP, 15ns tPD DESCRIPTION Commercial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Commercial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% Industrial temp range, 3.3 volt power supply, 10% DRAWING NUMBER SOT187-2 SOT187-2 SOT187-2 SOT187-2 SOT376-1 SOT376-1 SOT376-1 SOT376-1 SOT188-3 SOT188-3 SOT188-3 SOT188-3 SOT189-3 SOT189-3 SOT189-3 SOT189-3 SOT382-1 SOT382-1 SOT382-1 SOT382-1
XPLATM ARCHITECTURE
Figure 1 shows a high level block diagram of a 64 macrocell device implementing the XPLATM architecture. The XPLATM architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunnerTM family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the 6 control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has 5 dedicated product terms from the PAL array. The pin-to-pin tPD of the PZ3064 device through the PAL array is 10ns. If a macrocell needs more than 5 product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the total pin-to-pin tPD for the PZ3064 using 6 to 37 product terms is 12.5ns (10ns for the PAL + 2.5ns for the PLA).
1997 Mar 05
83
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
MC0 MC1 I/O MC15 16 16 ZIA MC0 MC1 I/O MC15 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK
MC0 MC1 I/O MC15
MC0 MC1 I/O MC15
SP00439
Figure 1. Philips XPLA CPLD Architecture
36 ZIA INPUTS
CONTROL
6
5
PAL ARRAY
PLA ARRAY
(32)
TO 16 MACROCELLS
SP00435
Figure 2. Philips Logic Block Architecture
1997 Mar 05
84
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the CoolRunnerTM family. The macrocell consists of a flip-flop that can be configured as either a D or T type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunnerTM family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are 4 clocks available on the PZ3064 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other 4 control terms (CT2-CT5) can be used
to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunnerTM devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunnerTM devices also provide a Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails Testing". There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-Stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated.
TO ZIA
D/T INIT (P or R) CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3
Q
GTS GND CT0 CT1 GND CT2 CT3 CT4 CT5 VCC GND
SP00457
Figure 3. PZ3064 Macrocell Architecture
1997 Mar 05
85
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
Simple Timing Model
Figure 4 shows the CoolRunnerTM Timing Model. The CoolRunnerTM timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and tCO. In other competing architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLATM architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the PZ3064 device, the user knows up front that if a given output uses
5 product terms or less, the tPD = 10ns, the tSU_PAL = 6ns, and the tCO = 7ns. If an output is using 6 to 37 product terms, an additional 2ns must be added to the tPD and tSU timing parameters to account for the time to propagate through the PLA array.
TotalCMOSTM Design Technique for Fast Zero Power
Philips is the first to offer a TotalCMOSTM CPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer CPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 2 showing the IDD vs. Frequency of our PZ3064 TotalCMOSTM CPLD.
INPUT PIN
tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA
D
Q
REGISTERED tCO
OUTPUT PIN
CLOCK
SP00441
Figure 4. CoolRunnerTM Timing Model
100
80 IDD (mA) 60
TYPICAL
40
20
0 0 20 40 60 80 100 FREQUENCY (MHz)
SP00460A
Figure 5. IDD vs. Frequency @ VDD = 3.3V, 25C
Table 2. IDD vs. Frequency
VDD = 3.3V FREQUENCY (MHz) Typical IDD ( mA) 0 0.04 20 13 40 26 60 40 80 50 100 63
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86
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
ABSOLUTE MAXIMUM RATINGS4
SYMBOL VDD VI VOUT IIN IOUT TJ Tstr Supply voltage Input voltage Output voltage Input current Output current Maximum junction temperature Storage temperature PARAMETER MIN. -0.5 -1.2 -0.5 -30 -100 -40 -65 MAX. 7.0 VDD+0.5 VDD+0.5 30 100 150 150 UNIT V V V mA mA C C
NOTES: 4. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied.
OPERATING RANGE
PRODUCT GRADE Commercial Industrial TEMPERATURE 0 to +70C -40 to +85C VOLTAGE 3.3 10% V 3.3 10% V
1997 Mar 05
87
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0C Tamb +70C; 3.0V VDD 3.6V SYMBOL VIL VIH VI VOL VOH II IOZ IDDQ IDDD1 IOS CIN CCLK CI/O PARAMETER Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current 3-Stated output leakage current Standby current Dynamic current Short circuit output current Input pin capacitance Clock input capacitance I/O pin capacitance TEST CONDITIONS VDD = 3.0V VDD = 3.6V VDD = 3.0V, IIN = -18mA VDD = 3.0V, IOL = 8mA VDD = 3.0V, IOH = -8mA VIN = 0 to VDD VIN = 0 to VDD VDD = 3.6V, Tamb = 0C VDD = 3.6V, Tamb = 0C @ 1MHz VDD = 3.6V, Tamb = 0C @ 50MHz 1 pin at a time for no longer than 1 second Tamb = 25C, f = 1MHz Tamb = 25C, f = 1MHz Tamb = 25C, f = 1MHz 5 -5 2.4 -10 -10 10 10 50 1 40 -100 8 12 10 2.0 -1.2 0.5 MIN. MAX. 0.8 UNIT V V V V V A A A mA mA mA pF pF pF
NOTE: 1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES
Commercial: 0C Tamb +70C; 3.0V VDD 3.6V SYMBOL tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR PARAMETER Propagation delay time, input (or feedback node) to output through PAL Propagation delay time, input (or feedback node) to output through PAL & PLA Clock to out delay time Setup time (from input or feedback node) through PAL Setup time (from input or feedback node) through PAL + PLA Hold time Clock High time Clock Low time Input Rise time Input Fall time Maximum FF toggle rate2 (1/tCH + tCL) (1/tSUPAL + tCF) (1/tSUPAL + tCO) 125 91 80 1.5 8.5 11 5.5 50 12.5 12.5 15 15 Maximum internal frequency2 Maximum external frequency2 Output buffer delay time Input (or feedback node) to internal feedback node delay time through PAL Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time Delay from valid VDD to valid reset Input to output disable3 Input to output valid Input to register preset Input to register reset 4 4 20 20 100 74 67 1.5 10.5 13 6.5 50 14 14 16 16 -10 MIN. 2 3 2 5.5 8 0 5 5 20 20 MAX. 10 12.5 7 MIN. 2 3 2 7 9.5 0 -12 MAX. 12 14.5 8 UNIT ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1997 Mar 05 88
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: SYMBOL VIL VIH VI VOL VOH II IOZ IDDQ IDDD1 IOS CIN CCLK CI/O -40C Tamb +85C; 3.0V VDD 3.6V PARAMETER Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current 3-Stated output leakage current Standby current Dynamic current Short circuit output current Input pin capacitance Clock input capacitance I/O pin capacitance TEST CONDITIONS VDD = 3.0V VDD = 3.6V VDD = 3.0V, IIN = -18mA VDD = 3.0V, IOL = 8mA VDD = 3.0V, IOH = -8mA VIN = 0 to VDD VIN = 0 to VDD VDD = 3.6V, Tamb = -40C VDD = 3.6V, Tamb = -40C @ 1MHz VDD = 3.6V, Tamb = -40C @ 50MHz 1 pin at a time for no longer than 1 second Tamb = 25C, f = 1MHz Tamb = 25C, f = 1MHz Tamb = 25C, f = 1MHz 5 -5 2.4 -10 -10 10 10 50 1 40 -130 8 12 10 2.0 -1.2 0.5 MIN. MAX. 0.8 UNIT V V V V V A A A mA mA mA pF pF pF
NOTE: 1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS1 FOR INDUSTRIAL GRADE DEVICES
Industrial: SYMBOL tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR -40C Tamb +85C; 3.0V VDD 3.6V PARAMETER Propagation delay time, input (or feedback node) to output through PAL Propagation delay time, input (or feedback node) to output through PAL & PLA Clock to out delay time Setup time (from input or feedback node) through PAL Setup time (from input or feedback node) through PAL + PLA Hold time Clock High time Clock Low time Input Rise time Input Fall time Maximum FF toggle rate2 (1/tCH + tCL) (1/tSUPAL + tCF) (1/tSUPAL + tCO) 100 74 67 1.5 10.5 13 6.5 50 14 14 16 16 Maximum internal frequency2 Maximum external frequency2 Output buffer delay time Input (or feedback node) to internal feedback node delay time through PAL Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time Delay from valid VDD to valid reset Input to output disable3 Input to output valid Input to register preset Input to register reset 5 5 20 20 100 65 58 1.5 13.5 16 7.5 50 15 15 17 17 I12 MIN. 2 3 2 7 9.5 0 5 5 20 20 MAX. 12 14.5 8 MIN. 2 3 2 8 10.5 0 I15 MAX. 15 17.5 9 UNIT ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns
NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1997 Mar 05 89
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
SWITCHING CHARACTERISTICS
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
VDD
S1
COMPONENT R1 R2
R1
VALUES 390 390 35pF
C1
VIN VOUT
MEASUREMENT
R2 C1
S1 Open Closed Closed
S2 Closed Open Closed
tPZH tPZL tP
S2
NOTE: For tPHZ and tPLZ C = 5pF
SP00461A
VOLTAGE WAVEFORM
10.00 VDD = 3.3V, 25C +3.0V 90%
9.80
9.60 10% 0V 9.40 tR 9.20 tPD_PAL (ns) 1.5ns tF 1.5ns
9.00
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
8.80
Input Pulses
8.60
SP00368
8.40
8.20
8.00 1 2 4 8 12 16 NUMBER OF OUTPUTS SWITCHING
SP00462
Figure 6. tPD_PAL vs. Outputs Switching
Table 3. tPD_PAL vs. Number of Outputs Switching
VDD = 3.3V NUMBER OF OUTPUTS Typical (ns) 1 8.0 2 8.4 4 8.8 8 9.2 12 9.6 16 10.0
1997 Mar 05
90
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PIN DESCRIPTIONS PZ3064 - 44-Pin Plastic Leaded Chip Carrier
6 1 40
PZ3064 - 68-Pin Plastic Leaded Chip Carrier
9 1 61
7
39
10
60
LCC
LCC
17
29
26
44
18
28
27
43
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 *
Function IN1 IN3 VDD I/O-A0/CK3 I/O-A2 I/O-A5 I/O-A8 (TDI) I/O-A11 I/O-A12 GND I/O-A13 I/O-A15 I/O-B15 (TMS)* I/O-B13 VDD
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Function I/O-B10 I/O-B8 I/O-B4 I/O-B3 I/O-B2 I/O-B0/CK2 GND VDD I/O-C0/CK1 I/O-C2 I/O-C3 I/O-C4 I/O-C7 I/O-C8 GND
Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Function I/O-C13 I/O-C15 (TCK) I/O-D15 I/O-D13 VDD I/O-D12 I/O-D11 I/O-D8 (TDO) I/O-D7 I/O-D2 I/O-D0 GND IN0-CK0 IN2-gtsn
THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES.
SP00452A
PZ3064 - 44-Pin Thin Quad Flat Package
44 34 * 1 33
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Function IN1 IN3 VDD I/O-A0/CK3 I/O-A2 GND I/O-A3 I/O-A4 I/O-A5 I/O-A7 VDD I/O-A8 (TDI) I/O-A10 I/O-A11 I/O-A12 GND I/O-A13 I/O-A15 I/O-B15 (TMS)* I/O-B13 VDD I/O-B12 I/O-B11
Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Function I/O-B10 I/O-B8 GND I/O-B7 I/O-B5 I/O-B4 I/O-B3 VDD I/O-B2 I/O-B0/CK2 GND VDD I/O-C0/CK1 I/O-C2 GND I/O-C3 I/O-C4 I/O-C5 I/O-C7 VDD I/O-C8 I/O-C10 I/O-C11
Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Function I/O-C12 GND I/O-D13 I/O-C15 (TCK) I/O-D15 I/O-D13 VDD I/O-D12 I/O-D11 I/O-D9 I/O-D8 (TDO) GND I/O-D7 I/O-D6 I/O-D4 I/O-D3 VDD I/O-D2 I/O-D0 GND IN0/CK0 IN2-gtsn
THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES.
SP00454
QFP
11
23
12
22
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 *
Function I/O-A8 I/O-A11 I/O-A12 GND I/O-A13 I/O-A15 I/O-B15 (TMS)* I/O-B13 VDD I/O-B10 I/O-B8 I/O-B4 I/O-B3 I/O-B2 I/O-B0/CK2
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Function GND VDD I/O-C0/CK1 I/O-C2 I/O-C3 I/O-C4 I/O-C7 I/O-C8 GND I/O-C13 I/O-C15 (TCK) I/O-D15 I/O-D13 VDD I/O-D12
Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Function I/O-D11 I/O-D8 (TDO) I/O-D7 I/O-D2 I/O-D0 GND IN0/CK0 IN2-gtsn IN1 IN3 VDD I/O-A0/CK3 I/O-A2 I/O-A5
THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES.
SP00453
1997 Mar 05
91
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PZ3064 - 84-Pin Plastic Leaded Chip Carrier
11 1 75
PZ3064 - 100-Pin Plastic Quad Flat Package
100 81
12
74
1
80
LCC
QFP
32
54
30
51
33
53
31
50
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 *
Function IN1 IN3 VDD I/O-A0/CK3 I/O-A1 I/O-A2 GND I/O-A3 I/O-A4 I/O-A5 I/O-A6 I/O-A7 VCC I/O-A8 (TDI) I/O-A9 I/O-A10 I/O-A11 I/O-A12 GND I/O-A13 I/O-A14 I/O-B15 I/O-B15 (TMS)* I/O-B14 I/O-B13 VDD I/O-B12 I/O-B11
Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Function I/O-B10 I/O-B9 I/O-B8 GND I/O-B7 I/O-B6 I/O-B5 I/O-B4 I/O-B3 VDD I/O-B2 I/O-B1 I/O-B0/CK2 GND VDD I/O-C0/CK1 I/O-C1 I/O-C2 GND I/O-C3 I/O-C4 I/O-C5 I/O-C6 I/O-C7 VDD I/O-C8 I/O-C9 I/O-C10
Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Function I/O-C11 I/O-C12 GND I/O-C13 I/O-C14 I/O-C15 (TCK) I/O-D15 I/O-D14 I/O-D13 VDD I/O-D12 I/O-D11 I/O-D10 I/O-D9 I/O-D8 (TDO) GND I/O-D7 I/O-D6 I/O-D5 I/O-D4 I/O-D3 VDD I/O-D2 I/O-D1 I/O-D0 GND IN0/CK0 IN2-gtsn
THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES.
SP00455
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Function NC NC I/O-A6 I/O-A7 VDD I/O-A8 (TDI) NC I/O-A9 NC I/O-A10 I/O-A11 I/O-A12 GND I/O-A13 I/O-A14 I/O-A15 I/O-B15 (TMS)* I/O-B14 I/O-B13 VDD I/O-B12 I/O-B11 I/O-B10 NC I/O-B9 NC I/O-B8 GND NC NC I/O-B7 I/O-B6 I/O-B5 I/O-B4
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Function I/O-B3 VDD I/O-B2 I/O-B1 I/O-B0/CK2 GND VDD I/O-C0/CK1 I/O-C1 I/O-C2 GND I/O-C3 I/O-C4 I/O-C5 I/O-C6 I/O-C7 NC NC VDD I/O-C8 NC I/O-C9 NC I/O-C10 I/O-C11 I/O-C12 GND I/O-C13 I/O-C14 I/O-C15 (TCK) I/O-D15 I/O-D14 I/O-D13 VDD
Pin 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Function I/O-D12 I/O-D11 I/O-D10 NC I/O-D9 NC I/O-D8 (TDO) GND I/O-D7 I/O-D6 NC NC I/O-D5 I/O-D4 I/O-D3 VDD I/O-D2 I/O-D1 I/O-D0 GND IN0/CK0 IN2-gtsn IN1 IN3 VDD I/O-A0/CK3 I/O-A1 I/O-A2 GND I/O-A3 I/O-A4 I/O-A5
*
THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES.
SP00456
1997 Mar 05
92
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
Package Thermal Characteristics
Philips Semiconductors uses the Temperature Sensitive Parameter (TSP) method to test thermal resistance. This method meets Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC Package Databook. Thermal resistance varies slightly as a function of input power. As input power increases, thermal resistance changes approximately 5% for a 100% change in power. Figure 7 is a derating curve for the change in JA with airflow based on wind tunnel measurements. It should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. Also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. Package 44-pin PLCC 44-pin TQFP 68-pin PLCC 84-pin PLCC 100-pin PQFP 44.8C/W 60.8C/W 44.9C/W 34.7C/W 44.5C/W Figure 7. Average Effect of Airflow on JA JA
PERCENTAGE REDUCTION IN JA (%) 0
10
20
30
40 PLCC/ QFP 50 0 1 2 3 4 5 AIR FLOW (m/s)
SP00419A
1997 Mar 05
93
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1997 Mar 05
94
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm
SOT376-1
1997 Mar 05
95
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
1997 Mar 05
96
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC84: plastic leaded chip carrier; 84 leads; pedestal
SOT189-3
1997 Mar 05
97
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
QFP100: plastic quad flat package; 100 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm
SOT382-1
1997 Mar 05
98
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
NOTES
1997 Mar 05
99
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 Mar 05 100

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